Northrop Grumman HTS Materials and Device Development

Northrop Grumman Cryogenic Electronics:
High-Tc Superconductor Materials and Device Development

Josephson Junction Development

Review article on HTS Josephson Junction Development
Control of junction characteristics

High-resistance HTS Edge Junctions for Digital Circuits

First demonstrations of multilayer 77K SQUIDs for digital circuits

Step-Edge Grain-Boundary Junctions with integrated groundplanes
Edge SNS Junctions with integrated groundplanes
Most recent results on Multilayer Edge-SNS SQUIDs for Digital Circuits

Results on SNS Edge Junctions with Integrated Groundplanes
Junction Reproducibility and Uniformity for HTS digital circuits
Stability of YBCO-Based Josephson Junctions evaluated in collaboration with NIST and Magnesensors, Inc.
Edge SNS Junctions needed to increase the scale of integration
Bi-Crystal Junctions evaluated in collaboration with Argonne National Laboratory

HTS Circuit Demonstrations

Multilayer HTS Counting A/D Converter
YBCO Step-edge-grain-boundary junctions in a 65K Shift Register

Single-Flux-Quantum Circuits

HTS SFQ T-Flip Flop with Directly Coupled Readout in collaboration with TRW

Epitaxial Multilayer Film Structures

Enhanced Properties of Superconducting Thin Films

Oriented Yttria Inclusions in YBCO Films in collaboration with the Naval Research Laboratory
Corrosion-Resistant Substituted YBCO Films in collaboration with the University of Texas
Effect of Oxygen Over-Doping on Tc and rf surface resistance of YBCO films
Large-Area Films for Passive Microwave Devices
Film Growth on Vicinal Substrates in collaboration with USAF Wright Laboratory

Investigation of Alternative Superconductive Devices and Processing

New Three Terminal Vortex Flow Device
Ba-K-Bi-O Films and Tunnel Junctions
Laser Patterning of YBCO Film Structures in collaboration with U. of Rochester

Overview of Thin-Film Materials Requirements for analog and digital applications of HTS

Photo Caption: The Northrop Grumman Superconductor Deposition and Analysis Facility is a unique tool for development of multilayer HTS film structures. Samples can be transferred among five UHV chambers without exposure to atmosphere. An exposed surface would form a reaction layer at the surface with a thickness comparable to the superconducting coherence length, the critical length scale determining performance of many superconducting devices including Josephson junctions. This permits clean surfaces and interfaces to be formed, preserved, and analyzed by XPS, AES, RHEED and LEED - analytical techniques well suited to the critical device length scales.

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Northrop Grumman Cryogenic Electronics: High-Tc Superconductor Materials and Device Development

Northrop Grumman Cryogenic Electronics:
High-Tc Superconductor Materials and Device Development